The present invention relates to a transistor of a semiconductor device and a method of fabricating the same. More particularly, the present invention relates to a transistor of a semiconductor device including a CMOS transistor and a method of fabricating the same.
A semiconductor device such as a dynamic random access memory (DRAM) has a cell region and a peripheral region. In the peripheral region, the semiconductor device uses complementary metal oxide semiconductor (CMOS) technology. Generally, in CMOS devices, a P-type MOS transistor has a buried channel structure. As the integration of the device has increased, a channel length in this buried channel structure is reduced. As a result, leakage current characteristics become degraded due to the high electric field. Accordingly, a dual gate structure having a symmetrical pair of N-type and P-type MOS transistors has been employed. The dual gate structure means a structure in which a P-type gate injecting P-type impurities is arranged where a PMOS transistor is to be formed and a N-type gate injecting N-type impurities is arranged where a NMOS transistor is to be formed.
However, the current in the PMOS transistor of the CMOS transistors may be reduced due to various reasons. For example, the amount of boron (B) in a source/drain region, which is a junction region of the PMOS transistor, may be decreased which reduces the PMOS current. The mobility of the PMOS transistor may also be decreased when the PMOS transistor is subjected to a tensile stress, thereby reducing the PMOS current.